1. Field of the Invention
The invention relates to a clock wiring technology, and more particularly to a clock design apparatus and a clock design method for designing the clock wiring of a semiconductor integrated circuit in which its clock frequency and supply voltage are changed.
2. Description of the Related Art
A method for realizing the lower power consumption of a semiconductor integrated circuit by changing the clock frequency and the supply voltage of a logical block in the semiconductor integrated circuit according to the workload has been in practical use. This method is characterized by changing the clock frequency and the supply voltage of the logical block to be lower than those in a normal state, when workload processed by the logical block is light. Since the clock frequency and the supply voltage are changed to be lower, the above method is effective in reducing the power consumption of the logical block. Particularly, since the electric power consumed by charging and discharging an output load capacity is proportional to the square of the supply voltage, there is a great effect of reducing power consumption by changing the supply voltage to be lower. Further, a sub-threshold leakage current is reduced by changing the supply voltage to be lower. Therefore, there is also an effect in reducing the power consumption due to a leakage current.
It is effective to use a delay adjusting circuit in a low power consumption designing method for changing the supply voltage of the logical block. By using the delay adjusting circuit, a circuit in the logical block is operable even in a period during which the supply voltage value changes.
On the other hand, a semiconductor integrated circuit and its designing method for reducing the clock skew by referring to a delay value of the clock signal has been proposed (e.g., see JP Hei. 7-98617 A). However, the method disclosed in JP Hei. 7-98617 can cope with variations in the manufacture, but cannot reduce the clock skew in response to a delay of the clock signal caused by changing the supply voltage. That is, even if the method disclosed in JP Hei. 7-98617 A is applied to the clock design method for the semiconductor integrated circuit including the logical block in which its clock frequency and the supply voltage are changed according to the workload, the clock skew cannot be reduced.